10/40 GigE MAC+PCS cores enable an unprecedented wire-to-application latency for financial applications on Altera Stratix V-based hardware.
BittWare, the leader in Altera-based FPGA COTS boards announced today at the 2014 High Performance Computing Linux for Wall Street Show & Conference that they have entered into a Value-Added Reseller (VAR) agreement with Tamba Networks, a developer of low-latency, high-speed Intellectual Property (IP) cores for networking and financial applications. The Tamba Networks 1 to 400 Gigabit Universal Ethernet IP Core is one of the lowest latency and gate count solutions on the market, enabling a 10 GigE "FIFO+MAC+PCS" of approximately 25 ns in an Altera Stratix V FPGA. This significantly decreases the round-trip delay wire-to-wire. By narrowing their focus to the ethernet MAC and PCS - designing their own soft PCS core as opposed to the typical solution which uses the hard PCS core - Tamba Networks has optimized the design of both, bringing an extremely efficient solution to market and saving many nanoseconds of latency in the process.
"Many of our customers are looking for the lowest possible latency," stated Ron Huizen, Vice President of Systems & Solutions at BittWare. "Therefore, we are always seeking out industry-leading technology that can help. Tamba's MAC+PCS IP cores enable us to provide our customers with unprecedented wire-to-application ethernet latency."
"BittWare is the Altera FPGA hardware platform of choice for financial customer applications in networking, packet processing, and high performance computing solutions," stated Nad Karim, Vice President of Sales and Business Development at Tamba Networks. "Their PCI Express boards based on the Altera Stratix V FPGA are an ideal fit for our MAC and PCS IP cores and we are very pleased to be partnering with them, giving our customers access to a complete solution."
The Tamba Networks IP cores are available today on all of BittWare's PCIe-based Altera Stratix V family of boards which include the following:
- S5PE-DS Dual Altera Stratix V GX/GS PCIe Board with Quad QSFP+, DDR3, QDRII+, and RLDRAM3
- S5PH-Q Altera Stratix V GX/GS Half-Length PCIe Board with Dual QSFP+/SFP+, DDR3, and QDRII+
- S5PE-F Altera Stratix V GX/GS PCI Board with VITA 57 FMC Site
- S5PE Altera Stratix V GX/GS PCI Board with Dual QSFP+
Universal Ethernet MAC Core Details:
- Full MAC layer and Reconciliation sub-layer implementation compliant with IEEE802.3
- PHY error and fault signaling provided by Reconciliation sub-layer
- CRC-32 insertion and checking at line-rate
- 100% bandwidth through implementation of Deficit Idle Counter (DIC)
- Configurable IPG with DIC from 1 byte to 48 bytes. Note, 12 bytes is the standard, and the default mode.
- Transmit Pad insertion.
- Full handling on transmit & receive FIFO overflow & underrun.
- Pause frame insertion on transmit and processing on receive.
- Jumbo frame support
- Transmit and Receive Statistics Vector
- Local Loopback