The industry leader with 77 nanosecond latency and highest throughput, Network Hardened, most mature and most widely adapted over the last 5 years, Intilop’s UDP/TCP Accelerators that are pre-integrated with OpenCL host kit provide an out-of-box working subsystem.
Intilop, Inc. a pioneer and a recognized leader in providing Ultra-Low latency networking Mega IP building blocks, systems and solutions, announced their 10G EMAC, UDP/TCP IP cores will be embedded in the OpenCL development kit and offered to end customers as a pre-integrated and system tested FPGA platform for Accelerated Networking systems. This offers a great value proposition for reduced development time and accelerated Time-to-Market.
Customers will be able to use the Altera SDK for OpenCL with Intilop’s UDP/TCP IP-Cores for implementing complex algorithms on FPGA accelerators for network enabled or low latency and high throughput applications. The Altera SDK for OpenCL combines the high level programming language of OpenCL and the massively parallel processing capabilities of the FPGA to deliver significantly higher system performance by abstracting away the traditional FPGA development and allowing software programmers access to the completely customizable FPGA. The industry leading Ultra-low-latency 10G TCP Offload with integrated OpenCL will be available soon.
“OpenCL” is an open, royalty-free standard for cross-platform, parallel programming of hardware accelerators, including CPUs, GPUs and FPGAs. The SDK for OpenCL enables software programmers to quickly and easily use the massively parallel and power efficient architecture of an FPGA to provide algorithm and upper layer protocol acceleration.
Intilop’s UDP, TCP Offload engines and other solutions are targeted towards end equipment makers that provide solutions to financial markets, web servers, email servers, high-end servers in Data centers, Network security, cloud computing, Government network systems and University campus network systems.