The HPC Platform HPME is based on a PCI Express (PCIe) board with a Stratix II GX FPGA that interfaces to several other boards with embedded QDRII memory and a Stratix II FPGA for acceleration (algorithmic processing). These boards are interfaced via 144 x 1-Gbps LVDS channels. With up to eight integrated transceiver channels and support for high-speed, low-latency memory access via a QDRII memory interface, the development board provides a fully integrated solution for multi-channel, high-performance applications, while also using limited board space.
Targeting key applications in the financial marketplace, the HPME looks for low-latency including feed handling and complex event processing (CEP) for algorithmic trading strategies, as well as Monte Carlo options and derivatives pricing and risk computations. Using full hardware processing, the HPME achieves performance with a latency of 1.1 to 2.0 microseconds in market data processing, including orders book management.
âWe have worked closely with Altera and leading investment banks to demonstrate ultra-low-latency feed handling and complex derivatives valuation acceleration as well as low-latency triggering of algorithmic trading CEP events,â said Marc Battyani, co-founder of HPC Platform. âOur appliances demonstrate the lowest latency available today. Traditional solutions can not efficiently address the ever-increasing growth in the complexity and volume of financial productsâ.
HPC Platformâs PCI Express board with a Stratix II GX provides a hardware platform for developing and prototyping high-performance PCIe-based designs and also demonstrates the embedded transceiver and memory circuitry of the Stratix II GX device. With its embedded transceivers, the Stratix II GX device can implement the entire PCIe interface on one device, and the development board offers a high-bandwidth, low-latency, power-efficient PCIe solution with sufficient logic elements (LEs) for these applications.
In the case of feed handling, there is a continuous race among key players to decrease the latency attached to the end-to-end CEP for algorithmic trading. The HPC Platform HPME leverages the ultra-low latency hardware-based feed handling to compute, analyze and deliver a real-time conclusion to another platform that is in a position to trigger an order execution. This processing is located within the feed handling function of the HPC Platform appliance and is performed at the same time with no additional latency due to events generation.
âThe HPC Platform appliances leverage the superior performance of our Stratix FPGA family by enabling hardware systems with the use of DSL compilers and optimized core librariesâ, said Dr. Misha Burich, Alteraâs senior vice president of research and development. âThese types of complex financial transactions have been easily and flexibly accelerated with FPGAs, while driving significant cost, power and space savings in the end system.â